1. Field of the Invention
The present invention relates generally to quad flat non-leaded (QFN) semiconductor packages, and more particularly, to a QFN semiconductor package capable of preventing solder extrusion and a method for fabricating the same.
2. Description of Related Art
In a QFN semiconductor package having a die pad and a plurality of leads, the bottom surfaces of the die pad and the leads are exposed from the semiconductor package such that the semiconductor package can be coupled to a printed circuit board through surface mount techniques, thereby forming a circuit module with a specific function. During such a surface mount process, the die pad and leads of the QFN semiconductor package are directly soldered to the printed circuit board.
As disclosed by U.S. Pat. No. 6,238,952, U.S. Pat. No. 6,261,864 and U.S. Pat. No. 6,306,685, a conventional QFN semiconductor package 8 is shown in FIG. 8.
The QFN semiconductor package 8 comprises: a lead frame 81 having a die pad 811 and a plurality of leads 813; a chip 83 mounted on the die pad 811; a plurality of bonding wires 84 electrically connecting to the chip 83 and the leads 813; and an encapsulant 85 encapsulating the chip 83, the bonding wires 84 and the lead frame 81, wherein the die pad 811 and the leads 813 protrude from the encapsulant 85 since the die pad 811 and the leads 813 are directly formed from a metal carrier by etching. Although such a method increases the number of I/O connections, it cannot form complex conductive traces.
FIGS. 9A to 9C′ show a conventional QFN semiconductor package 9 and a fabrication method thereof disclosed in U.S. Pat. No. 5,830,800 and No. 6,635,957. Referring to FIGS. 9A to 9C′, a plurality of leads 913 is formed on a metal carrier 90 by electroplating, wherein the leads 913 may be made of Au//Pd/Ni/Pd or Pd/Ni/Au; then, a plurality of chips 93 is mounted on the leads and electrically connected to the leads through bonding wires 94, and an encapsulant 95 is formed; thereafter, the carrier 90 is removed and a dielectric layer 96 is formed on the bottom surface of the encapsulant 95 and has a plurality of openings 961 formed therein such that a plurality of solder balls 97 can be mounted on the leads 913 exposed from the openings 961. However, since the solder balls 97 have good wetting ability on a gold layer or a palladium layer but the bonding between the dielectric layer 96 and the gold layer or palladium layer is quite poor, solder material can easily permeate into the interface between the gold layer or palladium layer and the dielectric layer 96, thereby resulting in occurrence of solder extrusion 962 that prevents formation of solder balls and even causes short circuits between adjacent solder balls. As such, subsequent SMT processes are adversely affected, fabrication time and cost are increased and the product yield is decreased.
Therefore, it is imperative to overcome the above drawbacks of the prior art.